Advanced Micro Devices (AMD)

Explore 108 Jobs at Advanced Micro Devices (AMD)

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Open Positions at Advanced Micro Devices (AMD)

Markham, Ontario, CA

Posted 2 days ago

The RTL IP Design Engineer develops block-level RTL IP and integrates embedded microprocessor subsystems for AMD SoC products. Responsibilities include design and debugging, verification and regression analysis, subsystem integration, and collaboration on specifications, test plans, and design signoff. The role also contributes to RTL methodologies and technical problem resolution.

Key Details

Top Skills Required

VerilogTclRuby +22 more
Markham, Ontario, CA (Hybrid)

Posted 2 days ago

The RTL Design Engineer will design and maintain block-level RTL IP and embedded microprocessor subsystems, including specifications, microarchitecture, integration, and verification. Responsibilities include debugging simulations and regressions, closing design and coverage issues, supporting verification plans, and coordinating IP releases and integration with SoC and validation teams.

Key Details

Top Skills Required

AXIFPGA EmulationMicroarchitecture +22 more

AMD seeks an experienced software architect specializing in Windows installation and deployment to design, develop, and maintain reliable installers and deployment solutions for desktop, device, and AI-enabled applications. The role includes building installer tools, supporting installation lifecycle and enterprise deployment scenarios, troubleshooting Windows installation issues, improving reliability and diagnostics, and integrating AI-assisted development tools.

Key Details

Top Skills Required

IntuneCPython +20 more

The Senior ASIC RTL Design Engineer will develop synthesizable RTL for networking and communications IP cores used in advanced AMD products. Responsibilities include collaborating with architecture, verification, SoC integration, and physical design teams; supporting synthesis and timing closure; resolving simulation regression issues; and mentoring less experienced designers.

Key Details

Top Skills Required

AHBEthernetVerilog +22 more

The Sr. Manager Packaging Engineering leads execution of multiple advanced package design programs for Data Center GPU and MI products, overseeing schedule, quality, and cost while managing engineering teams and cross-functional partners. The role also advances package design methodologies, automation, and AI-enabled workflows to improve execution and deliver manufacturable, high-performance solutions.

Key Details

Top Skills Required

Cadence APDInfluencingRisk Management +22 more
Ottawa, Ontario, CA

Posted 2 days ago

The Program Manager leads key engineering initiatives from concept through execution, coordinating engineering and business stakeholders across development, validation, and delivery. Responsibilities include program planning and scheduling, resource and budget oversight, risk mitigation, and alignment across hardware, firmware, software, and driver teams.

Key Details

Top Skills Required

Agile DevelopmentHardware ValidationResource Planning +19 more

The IOHUB Design Verification Engineer will define verification strategy and scope, develop test plans, implement DRVR, and drive verification closure for IOHUB IP. The role partners with design and architecture teams to build verification components and coordinates with global teams on strategy and status.

Key Details

Top Skills Required

VerilogDesign VerificationVirtualization +15 more

This role involves leading the RTL design and management of Security IP (SECIP) subsystems at AMD, focusing on microprocessor architectures, hardware accelerators, and cross-functional collaboration. The position requires technical leadership in defining specifications, driving design optimization, and mentoring engineering teams to meet performance, power, area, and schedule targets across diverse SoC platforms.

Key Details

Top Skills Required

On-Chip Interconnect ProtocolsFormal VerificationTeam Management +22 more

Top Benefits

Paid Time Off (Vacation & Personal Days)Tuition Reimbursement +14 more

Own full-chip static timing analysis and timing closure for complex SoC designs through final signoff. Collaborate with physical design, synthesis/DFT, CAD, and methodology teams on timing convergence, clock strategy, signoff methods, and automation.

Key Details

Top Skills Required

Multi-Corner Multi-Mode Timing AnalysisSetup and Hold AnalysisDesign Rule Violation Signoff +13 more

The Client/dGPU Systems Design Engineer serves as ROCm Feature Enablement Technical Lead for client and discrete GPU programs. The role drives pre- and post-silicon planning, feature enablement, system validation, issue triage, debugging, and fix verification, while coordinating across hardware and software teams and improving validation through automation and process enhancements.

Key Details

Top Skills Required

Technical LeadershipHIPRoot-Cause Analysis +21 more

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