Sr Manager ASIC (FPGA)

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

Reporting to the Sr. Manager, ASIC Processor Complex group. As a Senior Manager,  ASIC FPGA Development you will lead a team of FPGA designers responsible for implementation of FPGA solutions for emulation and SW testing of the next-generation optical networking processor and client subsystems and lead the team in developing processes, infrastructure, tools and new initiatives.

• In collaboration with the processor and client teams you will concurrently manage several projects throughout their complete lifecycle, including developing resource estimates and schedules and maintaining resource profile views for the team for long-term planning.
• You will partner with architects, software designers, and hardware designers to ensure cross-functional communication and alignment of requirements
• You will provide leadership in design and verification methodology definition.
• You will develop and review design specs, register maps, and verification guides/plans and interact with FPGA, chip and tool vendors to influence technology roadmaps, ensuring support issues are raised and monitored
• You will play a key role relative to day-to-day management of employees, ensuring adherence to conventions and guidelines, quality of work and focus on continuous improvement related to development tools and processes.
• You will be responsible for all aspects of people management ranging from hiring, performance and career discussions and performance management.

• undefined

The Must Haves:

• Degree in computer or electrical coupled with extensive FPGA/ASIC or related experience as a developer and/or manager.
• System Verilog experience for both design and verification.
• Experience with AMD Vivado and or Altera Quartus.
• Knowledge of advanced verification methods (UVM).
• Extensive knowledge of networking standards and interface technologies.
• Proven ability to drive continuous improvements and manage change.
• Strong project management skills.

Pay Range: The salary range for this role is $164, 600 - $263, 000

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.