Explore 10 Jobs at Astera Labs

Physical Design Engineering Director

Astera Labs

Toronto, Ontario, CA

Posted 12 days ago

The Physical Design Engineering Director will lead and develop the Toronto physical design team and own physical design execution for connectivity ASICs from RTL through GDSII/tapeout. Responsibilities include floorplanning, place-and-route, timing closure, sign-off, cross-functional and vendor coordination, and establishing scalable design flows and quality practices.

Principal FW/SW Engineer

Astera Labs

Toronto, Ontario, CA (Remote)

Posted a month ago

The Principal Engineer will own embedded firmware and software across analog connectivity and Ethernet retimer platforms, spanning architecture, hardware abstraction, calibration, link management, diagnostics, validation, and customer deployment. The role also leads technical direction, cross-functional design and debug efforts, and mentoring for connectivity products serving AI infrastructure.

Principal Analog Mixed-Signal Design Engineer

Astera Labs

Toronto, Ontario, CA (Hybrid)

Posted a month ago

The Principal Analog Mixed-Signal Design Engineer will architect and design high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O products. The role owns designs from specification through silicon bring-up and validation, sets team design methodologies, partners across engineering functions, and mentors junior engineers.

Digital Design Manager

Astera Labs

Toronto, Ontario, CA (Hybrid)

Posted 2 months ago

Leads day-to-day DFT architecture and execution for signal-conditioning semiconductor products, supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging. Responsibilities include implementing and validating test strategies, supporting silicon readiness and production ramp, improving yield and diagnostics, and coordinating with cross-functional teams and external partners.

Senior Design Verification Engineer

Astera Labs

Toronto, Ontario, CA (Hybrid)

Posted 2 months ago

The Senior Design Verification Engineer develops and maintains scalable verification environments for complex connectivity silicon, including UVM and C/C++ integration. Responsibilities include creating tests and assertions, analyzing coverage, automating regressions, validating protocols, and collaborating with RTL teams to debug issues across simulation, co-simulation, and emulation.

Senior Digital Design Engineer

Astera Labs

Toronto, Ontario, CA (Hybrid)

Posted 2 months ago

The Senior Digital Design Engineer will design and integrate high-performance connectivity silicon for AI infrastructure, contributing across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration. The role includes block-level and full-chip design, design-quality and timing work, and collaboration with verification, physical design, DFT, firmware, and system teams.

Principal Hardware Applications Engineer – PCIe Switches (Scorpio)

Astera Labs

Vancouver, British Columbia, CA (Hybrid)

Posted 3 months ago

The Principal Hardware Applications Engineer will lead customer technical engagements and system design-in for Scorpio Smart Fabric Switches, supporting evaluation, bring-up, debug, and production deployment. The role also involves post-silicon validation, system integration, technical leadership across teams, mentoring, and developing customer-facing technical materials.

Senior Tools Development Engineer – COSMOS Platform Software

Astera Labs

Vancouver, British Columbia, CA (Hybrid)

Posted 3 months ago

The Senior Tools Development Engineer will develop and maintain COSMOS platform software, including desktop applications, command-line tools, automation frameworks, and utilities for configuring, monitoring, debugging, and validating Astera Labs products. The role involves software that interfaces with company silicon, improving testing and engineering productivity, debugging system-level issues, and collaborating with firmware, hardware, validation, and product engineering teams.

Technical Lead Physical Design Engineer

Astera Labs

Toronto, Ontario, CA

Posted 4 months ago

The Technical Lead Physical Design Engineer owns end-to-end static timing analysis and timing closure for connectivity ASICs, from RTL through sign-off. Responsibilities include developing timing constraints and budgets, managing multi-corner/multi-mode analysis, producing timing feedback and ECO guidance, and coordinating with design, physical design, RTL, and verification teams.

Sr. Principal Program Manager, ASIC Design

Astera Labs

Toronto, Ontario, CA (Hybrid)

Posted 4 months ago

The Sr. Principal Program Manager, ASIC Design owns cross-functional execution of advanced ASIC and subsystem programs from early planning through tapeout. Responsibilities include program planning and reporting, coordinating engineering teams and external partners, managing risks and trade-offs, and establishing scalable program practices across complex silicon development.